1. Field of the Invention
This invention relates to a Dynamic Random Access Memory (DRAM), and particularly to a DRAM having a stress testing means for applying a voltage stress, e.g., when defect screening is performed in a wafer state (i.e., the DRAM which is not separated from a semiconductor wafer).
2. Description of the Related Art
In a manufacturing process of semiconductor devices, in general, products are sorted into good ones and bad ones by a die-sorting test after a process for producing semiconductor wafers, and thereafter the good ones are accommodated in packages, thereby obtaining their final form. The packaged products are screened. This screening is performed so as to expose latent defectiveness in the products, thereby eliminating defective products and enhancing the reliability of the products. As a method of screening, burn-in is employed in many cases, in which electric-field acceleration and temperature acceleration can be simultaneously performed.
Published Unexamined Japanese Patent Application (Kokai) No. 3-35491 (corresponding to U.S. application Ser. No. 544,614) discloses a semiconductor memory suitable in a case where memory cells in a wafer stage are screened using a probe card and a prober before they are subjected to a die-sorting process. Each memory chip region of the semiconductor memory can be effectively screened in a short time.
Further, in many semiconductor memories, a noise-eliminating MOS transistor is connected between the connection node of each word line and an earth node. This transistor is provided for preventing the potential of a non-selected word line from floating in a precharge period or in an active period during normal operation of the memories, thereby preventing the level of the word line from exceeding the threshold voltage of the transfer gate transistor of a memory cell, and hence preventing the data of the memory cells from being lost.
When a voltage stress is applied to all the word lines selected at the time of screening, if the noise-eliminating transistor is on, a pass current will flow to the earth node from a voltage stress power source via the word lines and the noise-eliminating transistor.
Therefore, it is necessary to employ control means for controlling the noise-eliminating transistor, so as to simultaneously apply the voltage stress to all the word lines at the time of the voltage stress examination of a DRAM.
Further if a MOS transistor for the voltage stress examination is provided at the other end of each word line, the required chip area will be increased. Thus, it is desirable to minimize the area of that part of the chip region which is required for performing the voltage stress examination.